The present invention relates to the manufacture of printed circuits and, more particularly, to the manufacture of printed circuits wherein a solderable coating is selectively applied to particular desired areas of the circuit.
In the fabrication of printed circuits, it is well known to provide the circuit, at those locations such as through-holes, pads and surface mount areas at which electrical components such as transistors, capacitors, integrated circuits, and the like will later be connected via soldering, with a metal coating which promotes and preserves ready solderability of those areas. Typically, the metal coating so provided is solder itself. In addition, other areas of the circuit at which soldered connections will not later be made, and which are to be protected in the subsequent solder connection operation, are masked.
There are a number of processes for arriving at the desired pattern of solder-bearing and solder-masked areas on the printed circuit. In a typical process, a printed circuit laminate (e.g., a double sided printed circuit or a multilayer circuit having copper foil clad outer surfaces) has through holes drilled therein which are then metallized via electroless copper depositing (at the same time providing electroless copper over the copper foil cladding). A plating resist pattern is then applied by selective exposure and development of a photoresist, the pattern being in the negative of the eventually desired conductive circuitry. Thereafter, copper thickness is built up at those areas not covered by the plating resist, typically by electrolytic copper plating. The built up copper areas are then overplated with electrolytic tin-lead to serve as an etch resist, the plating resist then removed, and the copper which was under the plating resist then etched away down to the substrate surface.
At this stage in the process, a number of different variations are possible for providing the ultimately desired solderable holes, pads and surface mount areas. For example, all areas of the board other than through-holes, pads and surface mount areas might at this point be covered with a solder mask, and then the tin-lead coating over the non-masked areas reflowed and fused to provide the requisite solder surface thereon. Generally, however, processing in this manner is not preferred because during the reflow and fusing, as well as during later connection of electrical devices via wave or dip soldering, the tin-lead coating on the copper traces under the solder mask tends also to reflow. This can result in the production of solder slivers, causing shorts between adjacent traces, and also can result in an aesthetically undesirable crinkled solder mask surface. One means to avoid this problem is to arrange that there be no reflowable metal under the solder mask, e.g., that any metal areas under the solder mask be bare copper surfaces (so-called SMOBC processes). Thus, after the copper etching step, the tin-lead etch resist is completely stripped, the areas other than holes, pads and surface mount areas then solder masked (the mask thus being over bare copper traces), and solder then applied to the exposed copper through-holes, pads, etc. by immersion tin-lead plating (followed by reflow and fusing) or, more typically, hot air solder leveling application.
Other techniques along these lines are known, such as the use of organic etch resists over tin-lead plated through-holes, pads, etc., followed by selective stripping of tin-lead from copper traces before application of solder mask. See U.S. Pat. No. 4,978,423 to Durnwith, Jr., et al. See also U.S. Pat. No. 4,325,780 to Schulz, Sr.; U.S. Pat. No. 4,487,654 to Coppin; and U.S Pat. No. 4,804,615 to Larson, et al for other known selective solder and solder masking processes which involve the use of multiple plating resists in attempts to only selectively provide tin-lead at desired locations.
In most of these known processes, then, for providing solder at desired hole, pad and surface mount locations, and for providing solder mask over bare copper traces, there is involved application of tin-lead to areas from which the tin-lead eventually is completely or selectively etched. This manner of processing involves wasteful use of tin-lead, adds tin-lead stripping requirements to the overall process, and requires processing of stripped tin-lead. In those other known processes which attempt to selectively provide tin-lead initially only to the areas eventually requiring solder coating, the foregoing problems are resolved but other problems are introduced in terms of the increased number of steps and expense in applying and then removing copper plating resists prior to application of the tin-lead plating resists which enable selective tin-lead plating, and/or in applying resists over existing resists and the problems attendant with imaging and exposure in such situations.
It is the primary object of the present invention to provide a process which eliminates problems of the type above-described.